Direct Generation of Upsampled FIR Filter Response A Simple Extension to Filters with Distributed Arithmetic
10th International Conference on Digital Technologies, Zilina, Slovakya, 9 - 11 Temmuz 2014, ss.110-113, (Tam Metin Bildiri)
- Yayın Türü: Bildiri / Tam Metin Bildiri
- Cilt numarası:
- Doi Numarası: 10.1109/dt.2014.6868700
- Basıldığı Şehir: Zilina
- Basıldığı Ülke: Slovakya
- Sayfa Sayıları: ss.110-113
- Eskişehir Osmangazi Üniversitesi Adresli: Evet
Özet
A memory based upsampling/interpolating FIR filter modification/extension to distributed arithmetic (DA) based FIR filters is proposed that can be used for any filter coefficient set. Use of minimum or no multiplier is a desired design property when signal processing is performed using FPGAs since multipliers are scarce/expensive resources within FPGAs whereas registers and such are abundant. Upsampling a digital stream is usually performed by inserting zeros between original samples followed by a low pass filter to reject images. Compared to basic distributed arithmetic based filter designs where partial products/sums are stored in memory blocks, our design stores interpolation values. These samples are output sequentially using a simple counter, eliminating zero insertions and saving circuit elements. As an example FIR filter, we have designed a raised-cosine band-limiting filter with example roll-off factor and upsampling values. Successful implementation using VHDL+FPGA with ease has proven that the approach is a simple and effective compared to input upsampling.